Silicon on Ceramics - A New Concept for Micro-Nano-Integration on Wafer Level

LTCC (low temperature cofired ceramics) are established materials for “System in Package” solutions due to the integration of passive elements, such as capacitors or resistors, associated with short development times as well as simple and cheap processing. The advantages of reliability, thermal stability and chemically inert packages offered by ceramic interconnect devices are combined with thin film precision by means of a smart wafer level packaging process. Tough mechanical, electrical or fluidic coupling of nano elements without affecting their functionality is guaranteed by a fully silicon-ceramic wafer compound material. The method is based on a bonding procedure between a nano patterned silicon surface (modified Black Silicon) and LTCC. A LTCC tape with adapted TCE to silicon is joined with a silicon wafer by lamination and pressure assisted firing.

This manufactured “Silicon-On-Ceramic”-substrate enables a wide range of design solutions, in witch several, unfired ceramic layers are prepared with vias, wirings and fluidic channels using standard LTCC-technologies. After sintering, the ceramic acts as a carrier system with electrical and fluidic properties. To ensure the electronic functionality of MEMS devices only a thin silicon layer is necessary. Fig. 1 illustrates the scheme of this new concept for micro-nano-integration.

Fig. 1: Work flow of the integration concept

The uniformly distributed silicon nano structure is generated by a self organized reactive ion etching process (Fig. 2a). During the lamination, the nano patterned wafer surface penetrates into the ductile, unfired LTCC tape. Due to the highly increased surface area, a form-fit bonding and a material connection between the glass phase of BGK and the silicon is generated during the firing step (Fig. 2b).The separation of silicon areas can easily be done by standard silicon etching processes such as DRIE or RIE, in which the ceramic works as a natural etching barrier (Fig. 2c).

Fig. 2: Nano patterned silicon before firing (a), Bond interface after firing (b), Chip separation by plasma etching (c)

Currently, we are able to fabricate a tight and high strength crack free silicon ceramic substrate compound in a standard 4 inch wafer format. Using this novel integration concept electrical contacts as well as fluidic components from nm to mm scale can be fabricated in one batch.